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HD6473032F Datasheet, PDF (450/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer
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Table 17-6 Timing of On-Chip Supporting Modules (cont)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
SCI
Ports
and
TPC
Transmit data
delay time
Receive data
setup time
(synchronous)
Receive data
hold time
(synchronous
clock input)
Receive data
hold time
(synchronous
clock output)
Output data
delay time
Input data
setup time
(synchronous)
Input data
hold time
(synchronous)
Symbol
tTXD
Condition A
8 MHz
Min Max
—
100
Condition B
10 MHz
Min Max
—
100
Condition C
16 MHz
Min Max
—
100
Test
Unit Conditions
ns Figure 17-15
tRXS
100 —
100 —
100 —
tRXH
100 —
100 —
100 —
tRXH
0
—
0
—
0
—
tPWD
tPRS
—
100 —
100 —
100 ns Figure 17-11
50
—
50
—
50
—
tPRH
50
—
50
—
50
—
435
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