HD6473032F Datasheet, PDF (384/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Restrictions in Synchronous Mode: When an external clock source is used in synchronous
mode, after TDR is reset, wait at least 5 clock counts (5ø) before inputting the transmit clock. If
the clock is input four states after the reset of TDR or earlier, an operation error may occur (figure
11-22).
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: When using an external clock, make sure t is 5 clock cycles or greater.
Figure 11-22 Transmission in Synchronous Mode (Example)
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