HD6473032F Datasheet, PDF (220/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

8.3 CPU Interface
8.3.1 16-Bit Accessible Registers
The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 8-6 and 8-7 show examples of word access to a timer counter (TCNT). Figures 8-8, 8-9,
8-10, and 8-11 show examples of byte access to TCNTH and TCNTL.
On-chip data bus
H
CPU L
Bus interface
H
L
Module
data bus
TCNTH TCNTL
Figure 8-6 Access to Timer Counter (CPU Writes to TCNT, Word)
On-chip data bus
H
CPU L
Bus interface
H
L
Module
data bus
TCNTH TCNTL
Figure 8-7 Access to Timer Counter (CPU Reads TCNT, Word)
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