HD6473032F Datasheet, PDF (169/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

7.10.2 Register Descriptions
Table 7-15 summarizes the registers of port A.
Table 7-15 Port A Registers
Address*
Name
H'FFD1
Port A data direction register
H'FFD3
Port A data register
Note: * Lower 16 bits of the address.
Abbreviation R/W
PADDR
W
PADR
R/W
Initial Value
H'00
H'00
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PA₇ DDR PA₆ DDR PA₅ DDR PA₄ DDR PA₃ DDR PA₂ DDR PA₁ DDR PA₀ DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input pin
if this bit is cleared to 0.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a PADDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
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