HD6473032F Datasheet, PDF (85/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

4.3 Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ₀ to IRQ₄) and
21 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
integrated timer unit (ITU), serial communication interface (SCI), and A/D converter. Each
interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Interrupts
External interrupts ^{NMI (1)}
IRQ₀ to IRQ₄ (5)
Internal interrupts
WDT^* (1)
ITU (15)
SCI (4)
A/D converter (1)
Note: Numbers in parentheses are the number of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
Figure 4-4 Interrupt Sources and Number of Interrupts
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