HD6473032F Datasheet, PDF (188/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have
the structure shown in figure 8-2.
TCLKA to TCLKD
ø, ø/2, ø/4, ø/8
Clock selector
Comparator
Control logic
TIOCA₀
TIOCB₀
IMIA0
IMIB0
OVI0
Module data bus
Legend
TCNT:
Timer counter (16 bits)
GRA, GRB: General registers A and B (input capture/output compare registers) (16 bits × 2)
TCR:
Timer control register (8 bits)
TIOR:
Timer I/O control register (8 bits)
TIER:
Timer interrupt enable register (8 bits)
TSR:
Timer status register (8 bits)
Figure 8-2 Block Diagram of Channels 0 and 1 (for Channel 0)
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