HD6473032F Datasheet, PDF (566/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Appendix D Pin States
D.1 Port States in Each Mode
Table D-1 Port States
Pin
Name
Mode
Reset
State
Hardware Software
Standby Standby
Mode
Mode
Sleep
Mode
Program
Execution
Sleep Mode
ø
—
Clock output T
H
Clock output Clock output
P1₇ to P1₀ 1
T
T
keep
keep
Input port
(DDR = 0)
—
—
T
keep
A₇ to A₀
(DDR = 1)
2, 3
T
T
keep
keep
I/O port
P2₇ to P2₀ 1
T
T
keep
keep
Input port
(DDR = 0)
—
—
T
keep
A₁₅ to A₈
(DDR = 1)
2, 3
T
T
keep
keep
I/O port
P3₇ to P3₀ 1
2, 3
T
T
T
T
D₇ to D₀
T
T
keep
keep
I/O port
P5₃ to P5₀ 1
T
T
keep
keep
Input port
(DDR = 0)
—
—
T
keep
A₁₉ to A₁₆
(DDR = 1)
2, 3
T
T
keep
keep
I/O port
P6₀
1 WAIT pin —
Generic T
I/O pin
—
T
T
T
T
T
WAIT
I/O port
2, 3
T
T
T
T
I/O port
P6₅ to P6₃ 1
2, 3
H
T
T
H
WR, RD, AS
T
T
keep
keep
I/O port
Legend
H: High
L: Low
T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
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