HD6473032F Datasheet, PDF (124/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

6.3.2 Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6-3 shows the timing of bus control signals for an 8-bit,
three-state-access area. Wait states can be inserted.
ø
Address bus
AS
Read
access
RD
D₇ to D₀
Write
access
WR
D₇ to D₀
Bus cycle
T₁
T₂
T₃
External address
Valid
Valid
Figure 6-3 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
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