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HD6473032F Datasheet, PDF (468/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer | |||
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Table A-1 Instruction Set (cont)
Addressing Mode and
Instruction Length (bytes)
No. of
States *1
Mnemonic
DIVXU. W Rs, ERd
DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
Operation
W ERd32 ÷ Rs16 âERd32
2
(Ed: remainder,
Rd: quotient)
(unsigned division)
B Rd16 ÷ Rs8 â Rd16
4
(RdH: remainder,
RdL: quotient)
(signed division)
W ERd32 ÷ Rs16 â ERd32
4
(Ed: remainder,
Rd: quotient)
(signed division)
B Rd8â#xx:8
2
B Rd8âRs8
2
W Rd16â#xx:16
4
W Rd16âRs16
2
L ERd32â#xx:32
6
L ERd32âERs32
2
B 0âRd8 â Rd8
2
W 0âRd16 â Rd16
2
L 0âERd32 â ERd32
2
W 0 â (<bits 15 to 8>
2
of Rd16)
L 0 â (<bits 31 to 16>
2
of Rd32)
W (<bit 7> of Rd16) â
2
(<bits 15 to 8> of Rd16)
L (<bit 15> of Rd32) â
2
(<bits 31 to 16> of
ERd32)
Condition Code
I HNZVC
ââ 6 7 ââ
22
ââ 8 7 ââ
16
ââ 8 7 ââ
24
⤠¤ ¤ ¤ ¤
2
⤠¤ ¤ ¤ ¤
2
â1 ¤ ¤ ¤ ¤
4
â1 ¤ ¤ ¤ ¤
2
â2 ¤ ¤ ¤ ¤
4
â2 ¤ ¤ ¤ ¤
2
⤠¤ ¤ ¤ ¤
2
⤠¤ ¤ ¤ ¤
2
⤠¤ ¤ ¤ ¤
2
ââ 0 ¤ 0 â
2
ââ 0 ¤ 0 â
2
ââ ¤ ¤ 0 â
2
ââ ¤ ¤ 0 â
2
453
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