HD6473032F Datasheet, PDF (170/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for
pins PA₇ to PA₀.
Bit
Initial value
Read/Write
7
PA ₇
0
R/W
6
PA ₆
0
R/W
5
PA ₅
0
R/W
4
PA ₄
0
R/W
3
PA ₃
0
R/W
2
PA ₂
0
R/W
1
PA ₁
0
R/W
0
PA ₀
0
R/W
Port A data 7 to 0
These bits store data for port A pins
When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is
returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level
is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
When port A pins are used for TPC output, PADR stores output data for TPC output groups 0 and
1. If a bit in the next data enable register (NDERA) is set to 1, the corresponding PADR bit cannot
be written. In this case, PADR can be updated only when data is transferred from NDRA.
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