HD6473032F Datasheet, PDF (570/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Reset in T₃ State: Figure D-3 is a timing diagram for the case in which RES goes low during the
T₃ state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus outputs are held during the T₃ state.The same timing applies when a reset occurs in
the T₂ state of an access cycle to a two-state-access area.
Access to external address
T₁
T₂
T₃
ø
RES
Internal
reset signal
Address bus
(mode 1)
AS (mode 1)
RD (read access)
(mode 1)
WR (write access)
(mode 1)
Data bus
(write access)
(mode 1)
I/O port
(modes 1 to 3)
H'000000
High impedance
High impedance
Figure D-3 Reset during Memory Access (Reset during T₃ State)
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