HD6473032F Datasheet, PDF (453/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

17.3 Operational Timing
This section shows timing diagrams.
17.3.1 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 17-4 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 17-5 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 17-6 shows the timing of the external three-state access cycle with one wait state
inserted.
438