HD6473032F Datasheet, PDF (177/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PB₇ DDR PB₆ DDR PB₅ DDR PB₄ DDR PB₃ DDR PB₂ DDR PB₁ DDR PB₀ DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin
if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a PBDDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores data for pins
PB7 to PB0.
Bit
Initial value
Read/Write
7
PB ₇
0
R/W
6
PB ₆
0
R/W
5
PB ₅
0
R/W
4
PB ₄
0
R/W
3
PB ₃
0
R/W
2
PB ₂
0
R/W
1
PB ₁
0
R/W
0
PB ₀
0
R/W
Port B data 7 to 0
These bits store data for port B pins
When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is
returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level
is read.
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
When port B pins are used for TPC output, PBDR stores output data for TPC output groups 2 and
3. If a bit in the next data enable register (NDERB) is set to 1, the corresponding PBDR bit cannot
be written. In this case, PBDR can be updated only when data is transferred from NDRB.
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