HD6473032F Datasheet, PDF (282/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Table 8-11 (d) ITU Operating Modes (Channel 3)
Register Settings
TSNC
TMDR
TFCR
TOCR TOER
TIOR3
TCR3
Operating Mode
Comple- Reset-
Output
Synchro-
mentary Synchro-
Level Master
nization MDF FDIR PWM
PWM
nized PWM Buffering XTGD Select Enable
IOA
Clear
Clock
IOB
Select
Select
Synchronous preset SYNC3 = 1 —
—o
o^*3
o
o
——
o^*1
o
o
o
o
PWM mode
o
—
— PWM3 = 1 CMD1 = 0 CMD1 = 0 o
——
o
—
o^*2
o
o
Output compare A
o
—
— PWM3 = 0 CMD1 = 0 CMD1 = 0 o
——
o
IOA2 = 0 o
o
o
Other bits
unrestricted
Output compare B
o
—
—o
CMD1 = 0 CMD1 = 0 o
——
o
o
IOB2 = 0 o
o
Other bits
unrestricted
Input capture A
o
—
— PWM3 = 0 CMD1 = 0 CMD1 = 0 o
——
EA3 ignored IOA2 = 1 o
o
o
Other bits Other bits
unrestricted unrestricted
Input capture B
o
—
— PWM3 = 0 CMD1 = 0 CMD1 = 0 o
——
EA3 ignored o
IOA2 = 1 o
o
Other bits
Other bits
unrestricted
unrestricted
Counter By compare o
clearing match/input
capture A
—
—o
Illegal setting: o^*4
o
CMD1 = 1
CMD0 = 0
——
o^*1
o
o
CCLR1 = 0 o
CCLR0 = 1
By compare o
match/input
capture B
—
—o
CMD1 = 0 CMD1 = 0 o
——
o^*1
o
o
CCLR1 = 1 o
CCLR0 = 0
Syn-
chronous
clear
SYNC3 = 1 —
—o
Illegal setting: o
CMD1 = 1
CMD0 = 0
o
——
o^*1
o
o
CCLR1 = 1 o
CCLR0 = 1
Complementary
o^*3
PWM mode
—
——
CMD1 = 1 CMD1 = 1 o
CMD0 = 0 CMD0 = 0
o^*6
o
o
—
—
CCLR1 = 0 o^*5
CCLR0 = 0
Reset-synchronized o
PWM mode
—
——
CMD1 = 1 CMD1 = 1 o
CMD0 = 1 CMD0 = 1
o^*6
o
o
—
—
CCLR1 = 0 o
CCLR0 = 1
Buffering
(BRA)
o
—
—o
o
o
BFA3 = 1 — —
o^*1
o
o
o
o
Other bits
unrestricted
Buffering
(BRB)
o
—
—o
o
o
BFB3 = 1 — —
o^*1
o
o
o
o
Other bits
unrestricted
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. Use the input capture A function in channel 1.
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