HD6473032F Datasheet, PDF (10/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Section 9 Programmable Timing Pattern Controller ......................................... 269
9.1 Overview ........................................................................................................................ 269
9.1.1 Features........................................................................................................... 269
9.1.2 Block Diagram................................................................................................ 270
9.1.3 TPC Pins ......................................................................................................... 271
9.1.4 Registers ......................................................................................................... 272
9.2 Register Descriptions...................................................................................................... 273
9.2.1 Port A Data Direction Register (PADDR) ...................................................... 273
9.2.2 Port A Data Register (PADR) ......................................................................... 273
9.2.3 Port B Data Direction Register (PBDDR) ...................................................... 274
9.2.4 Port B Data Register (PBDR) ......................................................................... 274
9.2.5 Next Data Register A (NDRA)....................................................................... 275
9.2.6 Next Data Register B (NDRB) ....................................................................... 277
9.2.7 Next Data Enable Register A (NDERA) ........................................................ 279
9.2.8 Next Data Enable Register B (NDERB)......................................................... 280
9.2.9 TPC Output Control Register (TPCR)............................................................ 281
9.2.10 TPC Output Mode Register (TPMR).............................................................. 284
9.3 Operation ........................................................................................................................ 286
9.3.1 Overview......................................................................................................... 286
9.3.2 Output Timing................................................................................................. 287
9.3.3 Normal TPC Output........................................................................................ 288
9.3.4 Non-Overlapping TPC Output........................................................................ 290
9.3.5 TPC Output Triggering by Input Capture....................................................... 292
9.4 Usage Notes .................................................................................................................... 293
9.4.1 Operation of TPC Output Pins........................................................................ 293
9.4.2 Note on Non-Overlapping Output .................................................................. 293
Section 10 Watchdog Timer ........................................................................................ 295
10.1 Overview ........................................................................................................................ 295
10.1.1 Features........................................................................................................... 295
10.1.2 Block Diagram................................................................................................ 296
10.1.3 Pin Configuration............................................................................................ 296
10.1.4 Register Configuration.................................................................................... 297
10.2 Register Descriptions...................................................................................................... 298
10.2.1 Timer Counter (TCNT)................................................................................... 298
10.2.2 Timer Control/Status Register (TCSR)........................................................... 299
10.2.3 Reset Control/Status Register (RSTCSR) ...................................................... 301
10.2.4 Notes on Register Access ............................................................................... 303
10.3 Operation ........................................................................................................................ 305
10.3.1 Watchdog Timer Operation............................................................................. 305
10.3.2 Interval Timer Operation ................................................................................ 306