HD6473032F Datasheet, PDF (426/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Section 16 Power-Down State
16.1 Overview
The H8/3032 Series has a power-down state that greatly reduces power consumption by halting
CPU functions. The power-down state includes the following three modes:
• Sleep mode
• Software standby mode
• Hardware standby mode
Table 16-1 indicates the methods of entering and exiting these power-down modes and the status
of the CPU and on-chip supporting modules in each mode.
Table 16-1 Power-Down State
State
Mode
Entering
Conditions
CPU
Supporting
I/O
Clock CPU Registers Functions RAM Ports
Exiting
Conditions
Sleep
mode
SLEEP instruc-
tion executed
while SSBY = 0
in SYSCR
Active
Halted Held
Active
Held Held
• Interrupt
• RES
• STBY
Software
standby
mode
SLEEP instruc-
tion executed
while SSBY = 1
in SYSCR
Halted
Hardware Low input at
standby STBY pin
mode
Halted
Halted
Halted
Held
Undeter
mined
Halted
and
reset
Halted
and
reset
Held
Held^*
Held
• NMI
• IRQ₀ to IRQ₂
• RES
• STBY
High
• STBY
impedance • RES
Note: * The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state
to hardware standby mode.
Legend
SYSCR: System control register
SSBY: Software standby bit
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