HD6473032F Datasheet, PDF (236/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Example of Synchronization: Figure 8-27 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0,
TIOCA1, and TIOCA2. For further information on PWM mode, see section 8.4.4, PWM Mode.
Value of TCNT0 to TCNT2 _{Cleared by compare match with GRB0}
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
TIOCA0
Time
TIOCA1
TIOCA2
Figure 8-27 Synchronization (Example)
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