HD6473032F Datasheet, PDF (133/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

6.4 Usage Notes
6.4.1 Register Write Timing
ASTCR and WCER Write Timing: Data written to ASTCR or WCER takes effect starting from
the next bus cycle. Figure 6-11 shows the timing when an instruction fetched from area 0 changes
area 0 from three-state access to two-state access.
T₁
T₂
T₃
T₁
T₂
T₃
T₁
T₂
ø
Address
ASTCR address
3-state access to area 0
2-state access
to area 0
Figure 6-11 ASTCR Write Timing
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