HD6473032F Datasheet, PDF (101/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ₀ to IRQ₄ interrupt requests.
Bit
7
6
5
4
3
2
1
0
—
—
— IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ ₄ to IRQ₀ enable
These bits enable or disable
IRQ₄ to IRQ₀ interrupts
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 4 to 0—IRQ₄ to IRQ₀ Enable (IRQ7E to IRQ0E): These bits enable or disable IRQ₄ to
IRQ₀ interrupts.
Bits 4 to 0
IRQ4E to IRQ0E
0
1
Description
IRQ₄ to IRQ₀ interrupts are disabled
IRQ₄ to IRQ₀ interrupts are enabled
(Initial value)
86