HD6473032F Datasheet, PDF (457/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

17.3.2 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 17-7 shows the reset input timing.
• Reset output timing
Figure 17-8 shows the reset output timing.
• Interrupt input timing
Figure 17-9 shows the input timing for NMI and IRQ₄ to IRQ₀.
ø
RES
t_RESS
t_RESS
t_RESW
Figure 17-7 Reset Input Timing
ø
RESO
t_RESD
t_RESD
t_RESOW
Figure 17-8 Reset Output Timing
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