HD6473032F Datasheet, PDF (280/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Table 8-11 (b) ITU Operating Modes (Channel 1)
Register Settings
TSNC
TMDR
TFCR
TOCR
TOER
TIOR1
TCR1
Reset-
Comple- Synchro-
Output
Synchro-
mentary nized Buffer-
Level Master
Clear
Clock
Operating Mode
nization MDF FDIR PWM
PWM PWM ing XTGD Select Enable IOA
IOB
Select
Select
Synchronous preset SYNC1 = 1 —
—o
—
—
—
—
—
—
o
o
o
o
PWM mode
o
—
— PWM1 = 1 —
—
—
—
—
—
—
o^*1
o
o
Output compare A
o
—
— PWM1 = 0 —
—
—
—
—
—
IOA2 = 0 o
o
o
Other bits
unrestricted
Output compare B
o
—
—o
—
—
—
—
—
—
o
IOB2 = 0 o
o
Other bits
unrestricted
Input capture A
o
—
— PWM1 = 0 —
—
—
o^*2
—
—
IOA2 = 1 o
o
o
Other bits
unrestricted
Input capture B
o
—
— PWM1 = 0 —
—
—
—
—
—
o
IOB2 = 1 o
o
Other bits
unrestricted
Counter By compare o
—
—o
—
—
—
—
—
—
o
o
CCLR1 = 0 o
clearing match/input
CCLR0 = 1
capture A
By compare o
—
—o
—
—
—
—
—
—
o
o
CCLR1 = 1 o
match/input
CCLR0 = 0
capture B
Syn-
SYNC1 = 1 —
—o
—
—
—
—
—
—
o
o
CCLR1 = 1 o
chronous
CCLR0 = 1
clear
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
2. Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode.
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