HD6473032F Datasheet, PDF (100/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ₀ to IRQ₄ interrupt
requests.
Bit
Initial value
Read/Write
7
—
0
R/(W)*
6
—
0
R/(W)*
5
—
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
Reserved bits
Note: * Only 0 can be written, to clear flags.
IRQ ₄ to IRQ₀ flags
These bits indicate IRQ₄ to IRQ₀
interrupt request status
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 0.
Bits 4 to 0—IRQ₄ to IRQ₀ Flags (IRQ4F to IRQ0F): These bits indicate the status of IRQ₄ to
IRQ₀ interrupt requests.
Bits 4 to 0
IRQ4F to IRQ0F
0
1
Note: n = 4 to 0
Description
[Clearing conditions]
(Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
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