HD6473032F Datasheet, PDF (132/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

6.3.4 Interconnections with Memory (Example)
For each area, the bus controller can select two- or three-state access. In three-state-access areas,
wait states can be inserted in a variety of modes, simplifying the connection of both high-speed
and low-speed devices.
Figure 6-10 shows an example of interconnections between the H8/3032 Series and memory.
Figure 6-10 shows a memory map for this example.
A 32-kword × 8-bit EPROM is connected to area 0. This device is accessed in three states via a 8-
bit bus.
Two 32-kword × 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 1. These
devices are accessed in two states via a 8-bit bus.
One 32-kword × 8-bit SRAM (SRAM3) is connected to area 7. This device is accessed via an
8-bit bus, using three-state access with an additional wait state inserted in pin auto-wait mode.
H'00000
H'0FFFF
H'10000
H'17FFF
H'18000
H'1FFFF
H'20000
H'2FFFF
H'30000
H'3FFFF
On-chip ROM
EPROM
Not used
SRAM1, 2
Not used
Area 0
8-bit, three-state-access area
Area 1
8-bit, two-state-access area
H'E0000
H'E7FFF
H'FFFFF
SRAM3
Not used
On-chip RAM
On-chip I/O registers
Area 7
8-bit, three-state-access area
(one auto-wait state)
Note: The bus width and the number of access states of the on-chip memories and registers
are fixed; they cannot be changed by register setting.
Figure 6-10 Memory Map (Example)
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