HD6473032F Datasheet, PDF (190/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Block Diagrams of Channels 3 and 4: Figure 8-4 is a block diagram of channel 3. Figure 8-5 is a
block diagram of channel 4.
TCLKA to
TCLKD
ø, ø/2,
ø/4, ø/8
Clock selector
Comparator
Control logic
TIOCA₃
TIOCB₃
IMIA3
IMIB3
OVI3
Module data bus
Legend
TCNT3:
Timer counter 3 (16 bits)
GRA3, GRB3: General registers A3 and B3 (input capture/output compare registers)
(16 bits × 2)
BRA3, BRB3: Buffer registers A3 and B3 (input capture/output compare buffer registers)
(16 bits × 2)
TCR3:
Timer control register 3 (8 bits)
TIOR3:
Timer I/O control register 3 (8 bits)
TIER3:
Timer interrupt enable register 3 (8 bits)
TSR3:
Timer status register 3 (8 bits)
Figure 8-4 Block Diagram of Channel 3
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