HD6473032F Datasheet, PDF (276/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T₃ state of a general register write cycle, input capture takes priority and the write to
the general register is not performed. See figure 8-68.
General register write cycle
T₁
T₂
T₃
ø
Address
GR address
Internal write signal
Input capture signal
TCNT
M
GR
M
Figure 8-68 Contention between General Register Write and Input Capture
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
f= ^ø
(N + 1)
(f: counter frequency. ø: system clock frequency. N: value set in general register.)
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