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HD6473032F Datasheet, PDF (449/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer
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Table 17-6 Timing of On-Chip Supporting Modules
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
ITU
SCI
Timer output
delay time
Timer input
setup time
Timer clock
input setup time
Timer Single
clock edge
pulse Both
width edges
Input Asyn-
clock chronous
cycle Syn-
chronous
Input clock rise
time
Input clock fall
time
Input clock
pulse width
Symbol
tTOCD
Condition A
8 MHz
Min Max
—
100
tTICS
50
—
tTCKS
50
—
tTCKWH 1.5
—
tTCKWL
2.5
—
tSCYC
4
—
tSCYC
6
—
tSCKR
—
1.5
tSCKF
—
1.5
tSCKW
0.4
0.6
Condition B
10 MHz
Min Max
—
100
Condition C
16 MHz
Min Max
—
100
50
—
50
—
50
—
50
—
1.5 —
1.5 —
2.5 —
2.5 —
4
—
4
—
6
—
6
—
—
1.5 —
1.5
—
1.5 —
1.5
0.4 0.6 0.4 0.6
Test
Unit Conditions
ns Figure 17-12
Figure 17-13
tCYC
Figure 17-14
tSCYC
434
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