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| HD6473032F Datasheet, PDF (267/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer | |||
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ø
TCNT
Overflow
signal
OVF
H'FFFF
H'0000
OVI
Figure 8-59 Timing of Setting of OVF
8.5.2 Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8-60 shows the timing.
TSR write cycle
T1
T2
T3
ø
Address
TSR address
IMF, OVF
Figure 8-60 Timing of Clearing of Status Flags
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