HD6473032F Datasheet, PDF (301/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

9.3 Operation
9.3.1 Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 9-2 illustrates the TPC output operation. Table 9-3 summarizes the TPC operating
conditions.
DDR
Q
NDER
Q
Output trigger signal
TPC output pin
C
Q DR D
Q NDR D
Internal
data bus
Figure 9-2 TPC Output Operation
Table 9-3 TPC Operating Conditions
NDER
DDR
Pin Function
0
0
Generic input port
1
Generic output port
1
0
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
1
TPC pulse output
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see
section 9.3.4, Non-Overlapping TPC Output.
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