HD6473032F Datasheet, PDF (222/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

On-chip data bus
H
CPU L
Bus interface
H
L
Module
data bus
TCNTH TCNTL
Figure 8-11 Access to Timer Counter (CPU Reads TCNT, Lower Byte)
8.3.2 8-Bit Accessible Registers
The registers other than the timer counters, general registers, and buffer registers are 8-bit
registers. These registers are linked to the CPU by an internal 8-bit data bus.
Figures 8-12 and 8-13 show examples of byte read and write access to a TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus
H
CPU L
Bus interface
H
L
Module
data bus
TCR
Figure 8-12 TCR Access (CPU Writes to TCR)
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