HD6473032F Datasheet, PDF (87/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

4.5 Stack Status after Exception Handling
Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7) ^→
Stack area
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
CCR
CCR *
PC _H
PC _L
Even address
Before exception handling
Save on stack
After exception handling
a. Normal mode
SP-4
SP-3
SP-2
SP-1
SP (ER7) ^→
Stack area
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
CCR
PC _E
PC _H
PC _L
Even address
Before exception handling
Save on stack
After exception handling
b. Advanced mode
Legend
PCE: Bits 23 to 16 of program counter (PC)
PCH: Bits 15 to 8 of program counter (PC)
PCL: Bits 7 to 0 of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: * Ignored upon return.
1. This is the address of the first instruction executed after return.
2. Saving and restoring of registers must be conducted at even addresses in word-size
or longword-size units.
Figure 4-5 Stack after Completion of Exception Handling
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