HD6473032F Datasheet, PDF (448/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Table 17-5 Control Signal Timing
Condition A: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_REF = 2.7 V to AV_CC,
V_SS = 0 V, ø = 2 MHz to 8 MHz, T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Condition B: V_CC = 3.0 V to 5.5 V, AV_CC = 3.0 V to 5.5 V, V_REF = 3.0 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 10 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Condition C: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 MHz to 16 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Item
RES setup time
RES pulse width
RESO output delay
time
RESO output pulse
width
NMI setup time
(NMI, IRQ₄ to IRQ₀)
NMI hold time
(NMI, IRQ₄ to IRQ₀)
Interrupt pulse width
(NMI, IRQ₄ to IRQ₀
when exiting software
standby mode)
Clock oscillator settling
time at reset (crystal)
Clock oscillator settling
time in software standby
(crystal)
Symbol
t_RESS
t_RESW
t_RESD
Condition A
8 MHz
Min Max
200 —
10
—
—
100
t_RESOW 132 —
t_NMIS
200 —
t_NMIH
10
—
t_NMIW
200 —
t_OSC1
20
—
t_OSC2
8
—
Condition B
10 MHz
Min Max
200 —
10
—
—
100
Condition C
16 MHz
Min Max
200 —
10
—
—
100
Unit
ns
t_CYC
ns
Test
Conditions
Figure 17-7
Figure 17-8
132 —
200 —
132
—
t_CYC
150 — ns Figure 17-9
10
—
10
—
200 —
200 —
20
—
20
— ms Figure 17-10
8
—
8
—
Figure 16-1
433