MC68HC908LB8_05 Datasheet, PDF (99/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
10.4.5 Variable Frequency Mode (HRPMODE = 0)
Variable frequency mode is selected when HRPMODE = 0. In this mode the period of the output signal
can be varied, while keeping the duty cycle fixed at 50%.
PERIOD1, PERIOD2, DUTY1, and DUTY2 are calculated from bits P[10:0] in registers
HRPPERH:HRPPERL to produce two frequencies having periods differing by one clock cycle but both
with 50% duty cycles. Table 10-2 lists the period and duty cycle values based on the HRPMODE bit.
The scaled value in STEP[4:0] (the five least significant bits of HRPPERH:HRPPERL) specifies how
many of the selected number of steps are spent on the longer period (PERIOD2). For more detailed
information, see 10.4.7 Dithering Controller.
The formula for calculating the average output period in variable frequency mode (including dithering) is:
Output Period (seconds) = --P-----^[--1---0----:-0----^]-- + ---I--N-----T----^⎝⎛---S--------T-2------E--^S------^EP----L------^[[--²--4--^:---^{0-:----]0--------]}--^⎠⎞----
HRPCLK _{-------3---2--------- ¥ HRPCLK}
2^SEL[2:0]
(EQ 10-1)
where the function INT() represents the integer part of the operand, and 2^SEL[2:0] is the STEP[4:0] scaling
factor.
In Variable Frequency Mode, the individual periods and duty cycles are given by:
PERIOD1 = ---P----[--1---0----:-0---]---
HRPCLK
(EQ 10-2)
DUTY1 = ^{P----E----R-----I--O----D----1--} = 50% duty cycle
2
(EQ 10-3)
59PERIOD2 = ^{P-----[-1----0---:--0---]---+-----1-}
HRPCLK
(EQ 10-4)
DUTY2 = ^{P----E----R-----I--O----D----2--} = 50% duty cycle
2
(EQ 10-5)
10.4.6 Variable Duty Cycle Mode (HRPMODE = 1)
Variable duty cycle mode is selected when HRPMODE = 1. This mode allows dithering to be achieved by
varying the duty cycle of the output waveform while keeping the period fixed.
In this mode, the period of both PERIOD1 and PERIOD2 are identical. DUTY2 is automatically set to
DUTY1 + 1. This provides two signals with the same frequency but with duty cycles differing by one bus
clock cycle. Dithering between these two signals can increase the resolution of the output by a factor of
up to 32.
The scaled value in STEP[4:0] (the five least significant bits of HRPDCH:HRPDCL) specifies how many
of the selected number of steps are spent on the longer duty cycle, DUTY2.
For more detailed information, see 10.4.7 Dithering Controller.
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
99