MC68HC908LB8_05 Datasheet, PDF (211/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

V_DD
10 kΩ*
0.1 µF
RST (PTA5)
Monitor Module (MON)
V_DD
V_DD
0.1 µF
1 µF
1 µF
DB9
2
3
5
1 _C1+
+
3 _C1–
4 _C2+
+
5 _C2–
7
8
MAX232
V_DD
16
+
1 µF
15
1 µF
+
9.8304 MHz CLOCK _{OSC1 (PTC0)}
V_TST
1 kΩ
V+ ²
V– ⁶
1 µF
10
9
V_DD
9.1 V
+
10 kΩ
74HC125
6
5
74HC125
2
3
4
IRQ (PTC2)
PTA0
1
V_DD
10 kΩ*
PTA1
10 kΩ*
PTA4
V_SS
* Value not critical
Figure 19-10. Normal Monitor Mode Circuit (External Clock, with High Voltage)
The monitor code has been updated from previous versions of the monitor code to allow enabling the
internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using
the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (4.0 MHz). Since this feature is enabled only
when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value
is not $FFFF) because entry into monitor mode in this case requires V_TST on IRQ.
Enter monitor mode with pin configuration shown in Figure 19-11 by pulling RST low and then high. The
rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
211