MC68HC908LB8_05 Datasheet, PDF (198/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Timer Interface Module (TIM)
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: $0025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
CH0F
0
CH0IE
MS0B
MS0A
ELS0B ELS0A
TOV0 CH0MAX
Reset:
0
0
0
0
0
0
0
0
Figure 18-10. TIM Channel 0 Status and Control Register (TSC0)
Address: $0028
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
CH1F
0
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Reset:
0
0
0
0
0
0
0
0
Figure 18-11. TIM Channel 1 Status and Control Register (TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x
status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
MC68HC908LB8 Data Sheet, Rev. 1
198
Freescale Semiconductor