MC68HC908LB8_05 Datasheet, PDF (177/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SIM Counter
cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively
pulls down the RST pin for all internal reset sources.
17.3.2.6 Monitor Mode Entry Module Reset (MODRST)
The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is
entered in the condition where the reset vectors are erased ($FF). When MODRST gets asserted, an
internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources.
17.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter is 13 bits long.
17.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
17.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal applications should use the full
stop recovery time, that is, with SSREC cleared.
17.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. See 17.6.2 Stop Mode for details. The SIM counter is
free-running after all reset states. See 17.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.
17.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
17.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 17-8 shows
interrupt entry timing. Figure 17-9 shows interrupt recovery timing.
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
177