MC68HC908LB8_05 Datasheet, PDF (206/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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19.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Address: $FE09
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: ^{Bit 15}
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
0
0
0
0
0
0
0
0
Figure 19-4. Break Address Register High (BRKH)
Address: $FE0A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: ^{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
0
0
0
0
0
0
0
0
Figure 19-5. Break Address Register Low (BRKL)
19.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
Address: $FE02
Bit 7
6
5
4
3
2
1
Read:
0
0
0
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 19-6. Break Auxiliary Register (BRKAR)
Bit 0
BDCOP
0
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt.
19.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
MC68HC908LB8 Data Sheet, Rev. 1
206
Freescale Semiconductor