MC68HC908LB8_05 Datasheet, PDF (208/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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19.3 Monitor Module (MON)
NOTE
For monitor entry, V_TST must be applied before V_DD.
This section describes the monitor module (MON) and the monitor mode entry methods. The monitor
module allows complete testing of the microcontroller unit (MCU) through a single-wire interface with a
host computer. Monitor mode entry can be achieved without use of the higher test voltage, V_TST, as long
as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit
programming.
Features include:
• Normal user-mode pin functionality on most pins
• One pin dedicated to serial communication between monitor read-only memory (ROM) and host
computer
• Standard mark/space non-return-to-zero (NRZ) communication with host computer
• Execution of code in random-access memory (RAM) or FLASH
• FLASH memory security feature⁽¹⁾
• FLASH memory programming interface
• Standard communication baud rate (9600 @ 9.8304 MHz external oscillator or 4 MHz generated
by internal oscillator)
• Simple monitor mode entry using internal oscillator
• 350 bytes monitor ROM code size ($FE20–$FF70)
• Monitor mode entry without high voltage, V_TST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
• Normal monitor mode entry if high voltage is applied to IRQ
19.3.1 Functional Description
Figure 19-9 shows a simplified diagram of the monitor mode entry.
The monitor module receives and executes commands from a host computer.
Figure 19-10, Figure 19-11, and Figure 19-12 show example circuits used to enter monitor mode and
communicate with a host computer via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
Table 19-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
• If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 9.8304 MHz
– IRQ = V_TST
1. No security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying the
FLASH difficult for unauthorized users.
MC68HC908LB8 Data Sheet, Rev. 1
208
Freescale Semiconductor