MC68HC908LB8_05 Datasheet, PDF (135/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Port A
Address:
Read:
Write:
Reset:
$0004
Bit 7
0
6
DDRA6
5
DDRA5
4
DDRA4
3
DDRA3
2
DDRA2
1
DDRA1
0
0
0
0
0
0
0
Figure 14-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA6–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA6–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 14-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
V_DD
DDRAx
PTAx
PTAPUEx
READ PTA ($0000)
INTERNAL
PULLUP
DEVICE
PTAx
Figure 14-4. Port A I/O Circuit
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 14-1 summarizes the operation of the port A pins.
Table 14-1. Port A Pin Functions
PTAPUE
Bit
1
0
X
DDRA
Bit
0
0
1
PTA
Bit
X⁽¹⁾
X
X
I/O Pin
Mode
Input, V_DD(2)
Input, Hi-Z⁽⁴⁾
Output
Accesses
to DDRA
Read/Write
DDRA6–DDRA0
DDRA6–DDRA0
DDRA6–DDRA0
Accesses
to PTA
Read
Write
Pin
PTA6–PTA0⁽³⁾
Pin
PTA6–PTA0⁽³⁾
PTA6–PTA0
PTA6–PTA0
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
135