MC68HC908LB8_05 Datasheet, PDF (104/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

High Resolution PWM (HRP)
10.5 Interrupts
Setting bits SHTIE and SHTEN SHTIF in the HRP control register (HRPCTRL) configures the SHTDWN
input to generate a CPU interrupt on detection of a falling edge or a low-level on the SHTDWN pin. The
interrupt remains set until both of these events occur:
• The interrupt flag, SHTIF, is cleared. SHTIF is cleared by writing a logic 0 to bit SHTIF in the
HRPCTRL register.
• Return of the SHTDWN pin to logic 1
NOTE
While the SHTDWN pin remains low, the interrupt request remains
pending.
10.6 Low-Power Modes
10.6.1 Wait Mode
The WAIT instruction puts the MCU in low power consumption standby mode. The HRP remains active
after the execution of a WAIT instruction. In Wait mode, the HRP registers are not accessible by the CPU.
Any enabled CPU interrupt request from the HRP can bring the MCU out of Wait mode. If HRP functions
are not required during Wait mode, reduce power consumption by disabling the HRP before executing the
WAIT instruction.
10.6.2 Stop Mode
The HRP is inactive after the execution of a STOP instruction. The TOP and BOT outputs are both set to
logic 0 after execution of the STOP instruction. Entering Stop mode causes the HRPEN bit in the
HRPCTRL register to be set to 0. When the MCU exits Stop mode after an external interrupt, the HRP
resumes operation.
NOTE
The HRP shutdown pin remains active during Stop mode.
10.7 HRP During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 19.2.2.5 Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state. To protect status
bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), software can read
and write I/O registers during the break state without affecting status bits. Some status bits have a
two-step read/write clearing procedure. If software does the first step on such a bit before the break, the
bit cannot change during the break state as long as BCFE is at 0. After the break, doing the second step
clears the status bit.
10.7.1 Input/Output Signals
Port B shares two of its pins with the HRP. The two output pins are PTB0/TOP and PTB1/BOT. Port C
shares one of its pins (PTC2/SHTDWN/IRQ) with the HRP.
MC68HC908LB8 Data Sheet, Rev. 1
104
Freescale Semiconductor