MC68HC908LB8_05 Datasheet, PDF (48/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Analog-to-Digital Converter (ADC)
3.6 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power consumption standby modes.
3.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
3.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC functionality resume when the MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.
3.7 I/O Signals
The ADC module has seven pins shared with ports A and B: PTB7/ADC6, PTA6/ADC5,
PTA4/ADC4–PTA0/ADC0.
V_ADIN is the input voltage signal from one of the seven ADC channels to the ADC module.
3.8 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADCLK)
3.8.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
Address:
Read:
Write:
Reset:
$003C
Bit 7
6
5
4
3
2
1
COCO
AIEN
ADCO ADCH4 ADCH3 ADCH2 ADCH1
0
0
0
1
1
1
1
Figure 3-3. ADC Status and Control Register (ADSCR)
Bit 0
ADCH0
1
COCO — Conversions Complete Bit
When the AIEN bit is a 0, the COCO is a read-only bit which is set each time a conversion is completed
except in the continuous conversion mode where it is set after the first conversion. This bit is cleared
whenever the ADSCR is written or whenever the ADR is read.
If the AIEN bit is a 1, the COCO becomes a read/write bit, which should be cleared to 0 for CPU to
service the ADC interrupt request. Reset clears this bit.
MC68HC908LB8 Data Sheet, Rev. 1
48
Freescale Semiconductor