MC68HC908LB8_05 Datasheet, PDF (109/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

HRP Registers
10.8.6 Frequency Dithering Control Register
This read/write register selects the clock source for the dithering controller, and selects the number of
dithering steps and modulus value of the dithering counter.
Address: $0059
Bit 15
Read:
Write:
Reset:
14
13
= Unimplemented
12
11
10
9
Bit 8
CLKSRC SEL2
SEL1
SEL0
0
0
0
0
Figure 10-15. Frequency Dithering Control Register (HRPDCR)
CLKSRC — Dithering Clock Source
This read/write bit selects the clock source for the 5-bit dithering counter.
1 = The dithering counter is clocked from the 16-bit timebase
0 = The dithering counter is clocked from the output of the dual frequency generator counter
Table 10-5
CLKSEL
0
Clock Source
Dual Frequency Generator
Timebase
----P----(--1---0---:--0---)----
HRPCLK
1
16 bit timebase
H-----R----P----T----B----H----:--H----R-----P----T---B----L--
HRPCLK
SEL[2:0] — Dithering Step/Modulus Select
These read/write bits select the number of steps used by the dithering counter and set the scaling
factor for the STEP[4:0] bits.
Table 10-6
SEL[2:0]
Number of Steps
0
32
1
16
2
8
3
4
4
2
5⁽¹⁾
0
6
Reserved
7
Reserved
NOTES:
1. No dithering occurs for this setting.
Divide STEP[4:0] by...
1
2
4
8
16
32
Reserved
Reserved
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
109