MC68HC908LB8_05 Datasheet, PDF (159/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Control Logic Block
15.8.7 Fault Control Register
The fault control register (FCR) controls the fault-protection circuitry.
Address: $0042
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
FINT FMODE
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-23. Fault Control Register (FCR)
FINT — Fault Interrupt Enable Bit
This read/write bit allows the CPU interrupt caused by faults on the fault pin to be enabled. The fault
protection circuitry is independent of this bit and will always be active. If a fault is detected, the PWM
pins will still be disabled according to the disable mapping register.
1 = Fault pin will cause CPU interrupts
0 = Fault pin will not cause CPU interrupts
FMODE — Fault Mode Selection for Fault Pin Bit (automatic versus manual mode)
This read/write bit allows the user to select between automatic and manual mode faults. For further
descriptions of each mode, see 15.5 Fault Protection.
1 = Automatic mode
0 = Manual mode
15.8.8 Fault Status Register
The fault status register (FSR) is a read-only register that indicates the current fault status.
Address:
Read:
Write:
Reset:
$0043
Bit 7
0
0
6
5
0
0
0
0
= Unimplemented
4
3
0
0
0
0
U = Unaffected
2
1
Bit 0
0
FPIN
FFLAG
0
U
0
Figure 15-24. Fault Status Register (FSR)
FPIN — State of Fault Pin Bit
This read-only bit allows the user to read the current state of the fault pin.
1 = Fault pin is at logic 1
0 = Fault pin is at logic 0
FFLAG — Fault Event Flag
The FFLAG event bit is set immediately when a rising edge is seen on the fault pin. To clear the FFLAG
bit, the user must write a 1 to the FTACK bit in the fault acknowledge register.
1 = A fault has occurred on the fault pin
0 = No new fault on the fault pin
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
159