MC68HC908LB8_05 Datasheet, PDF (149/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Fault Protection
NOTE
The terms “active” and “inactive” refer to the asserted and negated states
of the PWM signals and should not be confused with the high-impedance
state of the PWM pins.
Table 15-3. PWM Data Overflow and Underflow Conditions
PWMVALxH:PWMVALxL
$0000–$0FFF
$1000–$7FFF
$8000–$FFFF
Condition
Normal
Overflow
Underflow
PWM Value Used
Per register contents
$FFF
$000
15.4.3 Output Polarity
The output polarity of the PWMs is determined by the POLx bits. Positive polarity means that when the
PWM is active, the PWM output is high. Conversely, negative polarity means that when the PWM is
active, PWM output is low. See Figure 15-9.
EDGE-ALIGNED POSITIVE POLARITY
UP-ONLY COUNTER
MODULUS = 4
EDGE-ALIGNED NEGATIVE POLARITY
MODULUS = 4
PWM <= 0
PWM <= 0
PWM = 1
PWM = 1
PWM = 2
PWM = 2
PWM = 3
PWM = 3
PWM >= 4
PWM >= 4
Figure 15-9. PWM Output Polarity
15.5 Fault Protection
Conditions may arise in the external drive circuitry which require that the PWM signals become inactive
immediately. Furthermore, it may be desirable to selectively disable PWM(s) solely with software.
One or more PWM pins can be disabled (forced to their inactive state) by applying a logic high to the
external fault pin or by writing a logic high to either of the disable bits (DIS0 and DIS1 in PWM control
register 1). Figure 15-10 shows the structure of the PWM disabling scheme. While the PWM pins are
disabled, they are forced to their inactive state. The PWM generator continues
A fault can also generate a CPU interrupt. The fault pin has its own interrupt vector.
15.5.1 Fault Condition Input Pin
A logic high level on a fault pin disables the PWM(s) determined by the disable map bits (MAPx). The
external fault pin is software-configurable to re-enable the PWMs either with the fault pin (automatic
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
149