MC68HC908LB8_05 Datasheet, PDF (156/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Pulse Width Modulator with Fault Input (PWM)
NOTE
When PWMINT is cleared, pending CPU interrupts are inhibited.
PWMF — PWM Reload Flag
This read/write bit is set at the beginning of every reload cycle regardless of the state of the LDOK bit.
This bit is cleared by reading PWM control register 1 with the PWMF flag set, then writing a 0 to PWMF.
If another reload occurs before the clearing sequence is complete, then writing 0 to PWMF has no
effect.
1 = New reload cycle began
0 = New reload cycle has not begun
NOTE
When PWMF is cleared, pending PWM CPU interrupts are cleared (not
including fault interrupts).
LDOK— Load OK Bit
This read/write bit loads the prescaler bits of the PMCTL2 register and the entire PMMODH/L and
PWMVALH/L registers into a set of buffers. The buffered prescaler divisor, PWM counter modulus
value, and PWM pulse will take effect at the next PWM load. Set LDOK by reading it when it is 0 and
then writing a 1 to it. LDOK is automatically cleared after the new values are loaded or can be manually
cleared before a reload by writing a 0 to it. Reset clears LDOK.
1 = Load prescaler, modulus, and PWM values
0 = Do not load new modulus, prescaler, and PWM values
NOTE
The user should initialize the PWM registers and set the LDOK bit before
enabling the PWM. A PWM CPU interrupt request can still be generated
when LDOK is 0.
PWMEN — PWM Module Enable Bit
This read/write bit enables and disables the PWM generator and the PWM pins. When PWMEN is
clear, the PWM generator is disabled and the PWM pins are in the high-impedance state.
When the PWMEN bit is set, the PWM generator and PWM pins are activated.
For more information, see 15.6 Initialization and the PWMEN Bit.
1 = PWM generator and PWM pins enabled
0 = PWM generator and PWM pins disabled
15.8.5 PWM Control Register 2
PWM control register 2 (PCTL2) controls the PWM load frequency, PWM channel enabling/disabling, the
PWM polarity, the PWM correction method, and the PWM counter prescaler. For ease of software and to
avoid erroneous PWM periods, some of these register bits are buffered. The PWM generator will not use
the prescaler value until the LDOK bit has been set, and a new PWM cycle is starting. The load frequency
bits are not used until the current load cycle is complete.
See Figure 15-21.
NOTE
The user should initialize this register before enabling the PWM.
MC68HC908LB8 Data Sheet, Rev. 1
156
Freescale Semiconductor