MC68HC908LB8_05 Datasheet, PDF (223/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

5.0-Volt Control Timing
Characteristic⁽¹⁾
Symbol
Min
Typ⁽²⁾
Max
Unit
V_DD supply current
Run⁽³⁾
Wait⁽⁴⁾
Stop⁽⁵⁾
–40°C to 125°C⁽⁶⁾
–40°C to 125°C with LVI enabled⁽⁶⁾
—
18
25
mA
I_DD
—
12
15
mA
—
1
10
µA
—
140
300
µA
I/O ports Hi-Z leakage current⁽⁶⁾
I_IL
–10
—
+10
µA
Input current
I_In
–1
—
+1
µA
Pullup resistors (as input only)
Ports PTA6/KBD6–PTA0/KBD0, PTC2–PTC0, RST, IRQ
R_PU
16
26
36
kΩ
Capacitance
Ports (as input or output)
C_Out
C_In
—
—
—
—
12
8
pF
Monitor mode entry voltage
V_TST
V_{DD + 2.5}
—
9.1
V
Low-voltage inhibit, trip falling voltage
V_TRIPF
3.90
4.20
4.50
V
Low-voltage inhibit, trip rising voltage
V_TRIPR
4.00
4.30
4.60
V
Low-voltage inhibit reset/recover hysteresis
(V_TRIPF + V_HYS = V_TRIPR)
V_HYS
—
100
—
mV
POR rearm voltage⁽⁷⁾
V_POR
0
—
100
mV
POR reset voltage⁽⁸⁾
V_PORRST
0
700
800
mV
POR rise time ramp rate⁽⁹⁾
R_POR
0.035
—
—
V/ms
NOTES:
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_A (min) to T_A (max), unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) I_DD measured using external square wave clock source (f_OSC = 32 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I_DD. Measured with all modules enabled.
4. Wait I_DD measured using external square wave clock source (f_OSC = 32 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
I_DD. Measured with ICG and LVI enabled.
5. Stop I_DD is measured with OSC1 = V_SS.
6. Pullups and pulldowns are disabled. Port B leakage is specified in 20.8 5.0-Volt ADC Characteristics.
7. Maximum is highest voltage that POR is guaranteed.
8. Maximum is highest voltage that POR is possible.
9. If minimum V_DD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V_DD is reached.
20.6 5.0-Volt Control Timing
Characteristic⁽¹⁾
Internal operating frequency
Internal clock period (1/f_OP)
RST input pulse width low⁽²⁾
IRQ interrupt pulse width low⁽³⁾ (edge-triggered)
IRQ interrupt pulse period
Symbol
f_OP (f_Bus)
t_CYC
t_RL
t_ILIH
t_ILIL
Min
—
125
750
50
Note 5
Max
8
—
—
—
—
Unit
MHz
ns
ns
ns
t_CYC
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
223