MC68HC908LB8_05 Datasheet, PDF (182/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin or CPU interrupt
Figure 17-13. Wait Recovery from Interrupt
32
CYCLES
32
CYCLES
IAB
$6E0B
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
BUSCLKX4
Figure 17-14. Wait Recovery from Internal Reset
17.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset also causes an exit from stop mode.
The SIM disables the clock generator module outputs (BUSCLKX2 and BUSCLKX4) in stop mode,
stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask
option register (MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096
BUSCLKX4 cycles down to 32. This is ideal for applications using canned oscillators that do not require
long startup times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 17-15 shows stop mode entry timing.
Figure 17-16 shows stop mode recovery time from interrupt or break.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
MC68HC908LB8 Data Sheet, Rev. 1
182
Freescale Semiconductor