MC68HC908LB8_05 Datasheet, PDF (164/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Resets and Interrupts
• Releases the RST pin 32 BUSCLKX4 cycles after the oscillator stabilization delay
• Sets the POR bit in the SIM reset status register and clears all other bits in the register
OSC1
PORRST⁽¹⁾
BUSCLKX4
4096
32
CYCLES CYCLES
BUSCLKX2
RST PIN
1. PORRST is an internally generated power-on reset pulse.
Figure 16-1. Power-On Reset Recovery
16.2.3.2 Computer Operating Properly (COP) Reset
A computer operating properly (COP) reset is an internal reset caused by an overflow of the COP counter.
A COP reset sets the COP bit in the SIM reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
16.2.3.3 Low-Voltage Inhibit (LVI) Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the
LVI_TRIPF voltage.
An LVI reset:
• Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
BUSCLKX4 cycles after the power supply voltage rises to the LVI_TRIPF voltage
• Drives the RST pin low for as long as V_DD is below the LVI_TRIPF voltage and during the oscillator
stabilization delay
• Sets the LVI bit in the SIM reset status register
16.2.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal
opcode reset sets the ILOP bit in the SIM reset status register.
If the stop enable bit, STOP, in the CONFIG1 register is a 0, the STOP instruction causes an illegal
opcode reset.
16.2.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal
address reset sets the ILAD bit in the SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
MC68HC908LB8 Data Sheet, Rev. 1
164
Freescale Semiconductor