MC68HC908LB8_05 Datasheet, PDF (197/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 7
6
5
4
3
2
1
0
0
0
0
0
0
0
= Unimplemented
Figure 18-7. TIM Counter Registers Low (TCNTL)
I/O Registers
Bit 0
Bit 0
0
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
18.8.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: $0023
Bit 7
6
5
4
3
2
Read:
Write: ^{Bit 15}
14
13
12
11
10
Reset:
1
1
1
1
1
1
1
Bit 0
9
Bit 8
1
1
Figure 18-8. TIM Counter Modulo Register High (TMODH)
Address: $0024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Reset:
1
1
1
1
1
1
1
1
Figure 18-9. TIM Counter Modulo Register Low (TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
18.8.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
197