MC68HC908LB8_05 Datasheet, PDF (101/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
STEP[4:0] is read from register HRPPERL (if HRPMODE = 0) or from register HRPDCL (if HRPMODE =
1). See 10.4.4 Frequency Generation for more detailed information on the HRPMODE bit. Thus, by
varying the value of STEP[4:0], the programmer can vary the output signal.
10.4.8 Dithering Controller Timebase
The 5-bit counter may be clocked from the dual frequency generator counter or from a 16-bit timebase.
The clock source is selected by the CLKSRC bit in the HRPDCR register.
Clocking from the dual frequency generator sets the timebase for each dithering step equal to the period
of the HRP output waveform.
Clocking from the 16-bit timebase allows longer or shorter timebases to be used. This allows the system
designer to set the switching frequency to a certain value, to avoid undesirable harmonics or beat
frequencies.
Table 10-4 shows the clock options and corresponding timebase values.
Table 10-4. Dithering Timebase Options
CLKSEL
Clock Source
Timebase
0
Dual Frequency Generator
----P----(--1---0---:--0---)----
HRPCLK
1
16 bit timebase
H-----R----P----T----B----H----:--H----R-----P----T---B----L--
HRPCLK
10.4.9 Deadtime Insertion
The deadtime generators receive the two output signals TOP and BOT from the dual frequency generator
block.
Deadtime is incorporated into these signals on each positive edge by delaying the positive edge for a
number of clock cycles. The number of clock cycles is equal to the value in the 8-bit HRP Deadtime
register HRPDT. Figure 10-7 shows the relationship between the TOP and BOT input signals to the
deadtime generators, the HRPDT register contents, and the outputs from the deadtime generators.
MC68HC908LB8 Data Sheet, Rev. 1
Freescale Semiconductor
101