MC68HC908LB8_05 Datasheet, PDF (150/234 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Pulse Width Modulator with Fault Input (PWM)
mode) or with software (manual mode). The fault pin has an associated FMODE bit to control the PWM
re-enabling method. Automatic mode is selected by setting the FMODE bit in the fault control register.
Manual mode is selected when FMODE is clear.
The operation of the fault pin is asnynchronous. If it is enabled by either the MAP0 or MAP1 disable bits
and the fault pin goes high, the associated PWM(s) outputs are immediately disabled without waiting for
the next bus cycle.
The location of the fault pin is software configurable to one of two locations. Enabling the fault functionality
of a given pin does not disconnect that pin from any other module that is trying to use the pin.
CYCLE START
FMODE
LOGIC HIGH FOR FAULT
FAULT
PIN1
ONE
SHOT
CLEAR BY WRITING 1 TO FTACK
S Q _FFLAG
R
AUTO
MODE
MANUAL
MODE
FAULT PIN DISABLE
SQ
R
PWM DISABLE
FINT1
INTERRUPT REQUEST
Note:
In manual mode (FMODE = 0), fault may be cleared only if a logic level low at the input of the fault pin is present.
Figure 15-10. PWM Disabling Scheme
15.5.1.1 Automatic Mode
In automatic mode, the PWM(s) are disabled immediately once a fault condition is detected (logic high).
The PWM(s) remain disabled until the fault condition is cleared (logic low) and a new PWM cycle begins
as shown in Figure 15-11. Clearing the FFLAG event bit will not enable the PWMs in automatic mode.
FAULT PIN
PWM(S) ENABLED
PWM(S) DISABLED (INACTIVE)
PWM(S) ENABLED
Figure 15-11. PWM Disabling in Automatic Mode
The fault pin’s logic state is reflected in the FPIN bit. Any write to this bit is overwritten by the pin state.
The FFLAG event bit is set with each rising edge of the fault pin. To clear the FFLAG bit, the user must
write a 1 to the FTACK bit.
MC68HC908LB8 Data Sheet, Rev. 1
150
Freescale Semiconductor